Recently, direct-current to direct-current conversion (DC-DC) converters (power supply devices) that convert a given power supply voltage into a desired voltage and output the desired voltage have been widely used for various electronic devices such as a portable terminal. A fixed on-time DC-DC converter utilizing a bottom detection comparator method is proposed as such a DC-DC converter.
FIG. 1 is a block diagram schematically illustrating one example of a power supply device and a fixed on-time DC-DC converter utilizing a bottom detection comparator method.
In FIG. 1, the reference numeral 100 indicates a DC-DC converter (power supply device), the reference numeral 10 indicates an IC (semiconductor integrated circuit) for DC-DC conversion, the reference numeral 1 indicates an error comparator, and the reference numeral 102 indicates an on period (ton) generator.
Moreover, the reference numeral 3 indicates an RS flip flop, the reference numeral 4 indicates a drive logic circuit (a switching element control circuit), the reference numerals 51 and 52 indicate a first and a second switching transistors (nMOS transistors) respectively, the reference numeral 6 indicates a coil, and the reference numeral 7 indicates a smoothing capacitor.
As illustrated in FIG. 1, the power supply device 100 includes the semiconductor integrated circuit 10, the switching transistors 51 and 52, the coil 6, and the smoothing capacitor 7.
The transistors 51 and 52 are coupled in series between a high-potential power line to which a power supply voltage VIN is applied and a grounding wire to which a ground potential GND is applied. In the power supply device 100 illustrated in FIG. 1, the transistors 51 and 52 are provided outside of the semiconductor integrated circuit 10, however the transistors 51 and 52 may be provided inside of the semiconductor integrated circuit 10 as well.
The drive logic circuit 4 supplies a control signal DRVH to a gate of the transistor 51 and a control signal DRVL to a gate of the transistor 52 and thereby controls ON/OFF of the transistors 51 and 52.
A short period that turns off both the transistors 51 and 52 is inserted at switching, for example, by using an Anti Shoot Through (AST) circuit to prevent both transistors from turning on and to prevent a through-current from flowing.
A node LX (LX terminal) of the transistors 51 and 52 is coupled to an output terminal OUT of the power supply device 100 through the coil 6. The smoothing capacitor 7 is provided between the output terminal OUT and the grounding wire GND.
An equivalent series resistance (ESR) indicates parasitic resistance of the smoothing capacitor 7. The ESR may be provided as a separate resistor instead of as parasitic resistance.
The semiconductor integrated circuit 10 includes an error comparator 1, a ton generator 102, an RS flip flop 3, the drive logic circuit 4, and resistors R1, R2, and Rt.
The error comparator 1 compares a voltage FB, which is obtained by dividing an output voltage Vo at the resistors R1 and R2, with a reference voltage VREF, and supplies an output signal ERROUT to a set terminal S of the flip flop 3.
The ton generator 102 supplies an output signal TONOUT to a reset terminal R of the flip flop 3. An output signal Q of the flip flop 3, a power supply voltage VIN, an output voltage Vo, and a control signal DRVL of the transistor 52 etc. are supplied to the ton generator 102. The ton generator 102 is coupled to the grounding wire GND through the resistor Rt.
The fixed on-time DC-DC converter 100 utilizing a bottom detection comparator method with the above configuration controls an output voltage Vo by using a fixed on-time defined by a power supply voltage VIN and an output voltage Vo, and by using a ripple voltage in an output voltage Vo due to the ESR.
A current is supplied from the high potential power line through the transistor 51 during the on period “ton” (fixed on time). This increases a coil current ILX that flows in the coil 6 and raises the output voltage Vo, for example, due to parasitic resistance ESR of the smoothing capacitor 7.
As described above, it is ensured that the transistor 52 is turned off while the transistor 51 is turned on.
On the other hand, during an off period “toff”, energy accumulated in the coil 6 is supplied to a load Ro. This decreases a coil current IL that flows in the coil 6 and causes the output voltage Vo to drop due to the parasitic resistance ESR of the smoothing capacitor 7.
When a voltage obtained by dividing an output voltage Vo at the resistor R1 and the resistor R2 reaches a reference voltage VREF or less, an output signal ERROUT of the error comparator 1 becomes a high level “H”, and the RS flip flop 3 is set.
The Q output of the RS flip flop 3 becomes a high level “H”, and the period turns to the on period “ton” again. By repeating the on period “ton” and the off period “toff”, an average value of the output voltage Vo is maintained at a given level.
In other words, the error comparator 1 of the DC-DC converter 100 utilizing a bottom detection comparator method compares the divided output voltage Vo with the reference voltage VREF and controls duty during an off period “toff.” Accordingly, the DC-DC converter 100 stabilizes the output voltage Vo.
FIG. 2 is a circuit diagram illustrating one example of the ton generator 102 in the power supply device illustrated in FIG. 1. As illustrated in FIG. 2, the ton generator 102 includes resistors R31, R32, R51, and R52, comparators 21 and 27, pMOS transistors 22 and 23, an npn bipolar transistor 24, a capacitor 25, and an nMOS transistor 26.
A resistor Rt in FIG. 2 corresponds to the resistor Rt illustrated in FIG. 1 that is provided outside of the ton generator 102 in FIG. 1.
The comparator 21 compares a voltage obtained by dividing a power supply voltage VIN at the resistor R31 and the resistor R32 with an emitter voltage of the transistor 24, and supplies the output signal to a base of the transistor 24. This makes a given current I20 flow between the base and the emitter of the transistor.
A current I21 corresponding to the current I20 that flows through the transistor 24 flows through the transistor 23 by the current-mirror coupled transistors 22 and 23.
While the transistor 51 is turned on, electric charges from the current I21 are accumulated in the capacitor 25. When a voltage VCT from the capacitor 25 exceeds the voltage Vtref obtained by dividing the output voltage Vo at the resistors R51 and the R52, an output signal TONOUT of the comparator 27 is output.
This resets the RS flip flop 3, the Q output becomes a low level “L”, and the on period “ton” ends.
While the switching transistor 52 is turned on, in other words, the switching transistor 51 is turned off, the control signal DRVL is at a high level “H”, and thus the transistor 26 is turned on and no electric charge is accumulated in the capacitor 25.
Various DC-DC converters for outputting a voltage controlled to a given level have been proposed.
In the power supply device described by referring to FIGS. 1 and 2, the “on time” is fixed depending on the power supply voltage Vin and the output voltage Vo. Hence, output voltage characteristics such as regulation may be degraded when an output load current Io is changed.